1. Field of the Invention
The present invention relates to a dielectric isolation type semiconductor device with a high voltage circuit formed on a dielectric isolation type substrate, and to a manufacturing method therefor.
2. Description of the Related Art
In a known dielectric isolation semiconductor device, a dielectric layer and a rear surface electrode are arranged on an upper surface and a lower surface, respectively, of a support substrate, and a semiconductor substrate is provided on an upper surface of the dielectric layer so that the semiconductor substrate and the support substrate are dielectrically isolated from each other by means of the dielectric layer. An insulating film in the semiconductor substrate serves to define, in a prescribed range, an n− type semiconductor layer that constitutes the semiconductor substrate, and in this defined prescribed range, an n+ type semiconductor region having a resistance lower than that of the n− type semiconductor layer is formed on an upper surface of the n− type semiconductor layer, and a p+ type semiconductor region is also formed so as to surround the n+ type semiconductor region. In addition, a cathode electrode and an anode electrode are connected with the n+ type semiconductor region and the p+ type semiconductor region, respectively, and the cathode electrode and the anode electrode are insulated from each other by a field oxide film.
When both the anode electrode and the rear surface electrode are set to 0V with a positive voltage applied on the cathode electrode being gradually increased, there will develop a first depletion layer extending from a p-n junction between the n− type semiconductor layer and the p+ type semiconductor region. At this time, since the semiconductor substrate acts as a field plate through the dielectric layer, a second depletion layer in addition to the first depletion layer develops so as to extend in a direction toward the upper surface of the n− type semiconductor layer from an interface or boundary surface of the n− type semiconductor layer and the dielectric layer. Due to the extension of the second depletion layer, the first depletion layer become able to easily extend from the p-n junction toward the cathode electrode whereby an electric field at the p-n junction between the n− type semiconductor layer and the p+ type semiconductor region is alleviated. This effect is generally called a RESURF (reduced surface field) effect.
The electric field strength in the thickness direction of the n− type semiconductor layer at a position sufficiently away from the p+ type semiconductor region is zero in a range from an upper surface of the n− type semiconductor layer up to a prescribed position, increases linearly from the prescribed position, further increases in a stepwise manner at the interface or boundary surface of the n− type semiconductor layer and the dielectric layer, becomes constant in the dielectric layer, and returns to zero at a boundary between the dielectric layer and the support substrate. Representing the thickness of the depletion layer extending from the boundary between the n− type semiconductor layer and the dielectric layer by x, the thickness of the dielectric layer by t0, the impurity concentration of the n− type semiconductor layer by N(cm−3), the dielectric constant of a vacuum by ∈0 (C×V−1×cm−1), the relative dielectric constant of the n− type semiconductor layer by ∈2, and the relative dielectric constant of the dielectric layer by ∈3, respectively, a full voltage drop V in the thickness direction of the n− type semiconductor layer at a position sufficiently away from the p+ type semiconductor region is represented by the following expression (1).V=q·N/(∈2·∈0)×(x2/2+∈2·t0x/∈3)  (1)
From expression (1) above, it is found that when the thickness t0 of the dielectric layer is increased while keeping the full voltage drop V unchanged, the thickness x of the second depletion layer extending from the interface is decreased. This means the RESURF effect becomes weaker.
On the other hand, under the condition that avalanche breakdowns due to the concentration of electric field at the p-n junction between the n− type semiconductor layer and the p+ type semiconductor region and the concentration of electric field at the interface between the n− type semiconductor layer and the n+ type semiconductor region do not occur, the dielectric strength of the dielectric isolation type semiconductor device is eventually determined by the avalanche breakdown due to the concentration of electric field at the interface between the n− type semiconductor layer and the dielectric layer at a location right under the n+ type semiconductor region. In order to construct the dielectric isolation type semiconductor device so as to satisfy such a condition, the p+ type semiconductor region and the n+ type semiconductor region need only be arranged sufficiently away from each other so that the thickness and the impurity concentration of the n− type semiconductor layer can be optimized.
It is generally known that the condition for nonoccurrence of avalanche breakdowns means that state in which when depletion is caused from the interface between the n− type semiconductor layer and the dielectric layer to the upper surface of the n− type semiconductor layer, the concentration of electric field at the interface between the n− type semiconductor layer and the dielectric layer satisfies the avalanche breakdown condition.
Under such a condition, when the thickness of the n− type semiconductor layer is represented by d and the critical electric field that causes avalanche breakdown by Ecr, the dielectric strength V is shown by the following expression (2), while neglecting the thickness of the n+ type semiconductor region.V=Ecr·(d/2+∈2·t0/∈3)  (2)
Here, the dielectric strength V of the dielectric isolation type semiconductor device is calculated with the n− type semiconductor layer being formed of silicon, and the dielectric layer being formed of a silicon oxide film. D =4×10−4 and t0 =2×10−4 are adopted as general values for the distance d and the thickness t0, respectively. The critical electric field strength Ecr, though influenced by the thickness d of the n− type semiconductor layer, is represented in this case by about Ecr=4×105. With this, by assigning numeric values 11.7 and 3.9 to ∈2 and ∈3 (i.e., ∈2=11.7 and ∈3=3.9), respectively, the dielectric strength V is calculated as 320 V.
When the thickness d of the n− type semiconductor layer is increased by 1 μm, the dielectric strength increases by 20 V, and when the thickness t0 of the dielectric layer is increased by 1 μm, the dielectric strength increases by 120 V.
Thus, the dielectric strength increases more greatly when increasing the thickness of the dielectric layer than when increasing the thickness of the n− type semiconductor layer, so for the purpose of increasing of the dielectric strength, it is more effective to increase the thickness of the dielectric layer rather than that of the n− type semiconductor layer. Besides, to increase the thickness of the n− type semiconductor layer results in increased difficulty in the formation of the insulating film, and hence is undesirable.
On the other hand, when the thickness of the dielectric layer is increased, the extension of the second depletion layer becomes small as stated above, thus resulting in reduction in the RESURF effect. That is, the concentration of electric field at the p-n junction between the p+ type semiconductor region and the n− type semiconductor layer increases, whereby the dielectric strength will be limited by a possible avalanche breakdown at this p-n junction.
Accordingly, by forming a porous oxide film in a region of the support substrate including a portion right under the cathode electrode arranged on the upper surface of the n+ type semiconductor region of the semiconductor substrate, the concentration of electric field in the n− type semiconductor layer in the vicinity of the boundary of the n+ type semiconductor region and the n− type semiconductor layer is alleviated, and the dielectric strength is improved.
In addition, by forming a through hole in a region of the support substrate including a portion right under a drain electrode of a MOSFET formed on the semiconductor substrate, and forming a dielectric layer made of silicone ladder polymer on that portion of the dielectric layer which appears in the interior of the through hole, the concentration of electric field in the n− type semiconductor layer in the vicinity of the boundary of the n+ type semiconductor region and the n− type semiconductor layer is alleviated, and the dielectric strength is improved (see, for example, a first patent document: Japanese patent application laid-open No. 2004-200472).
However, when the dielectric strength of the dielectric isolation type semiconductor device increases due to the formation of the porous oxide film, the dielectric strength of lead-out wiring from the cathode electrode will fall below the dielectric strength of the dielectric isolation type semiconductor device. In view of this, by adopting wire wiring in place of the lead-out wiring from the cathode electrode, the dielectric strength can be made to exceed the dielectric strength of the semiconductor device.
However, when a wire is wire bonded to the cathode electrode right under which the porous oxide film is formed, by using an ultrasonic wire bonder, there will be a problem that an ultrasonic wave is applied to the sponge-like porous oxide film, thereby generating a crack therein.
Moreover, in the case where the through hole is formed through the support substrate, there is another problem that the dielectric isolation type semiconductor device might be caused to flex due to a force that is generated by a header of the ultrasonic wire bonder to urge the wire against the drain electrode.